My colleague asked me about this and I thought I’ll post it here. Let’s say you get an error like
ncvlog: *E,NOTCLM (myXtr.sv,62|29): Regrite_t is not a class item
You can do
% nchelp ncvlog NOTCLM
and you’ll get
nchelp: 12.20-s008: (c) Copyright 1995-2013 Cadence Design Systems, Inc.
ncvlog/NOTCLM =
The specified name is not an item (property or method, for example) in the class.
This works for ncelab as well
% nchelp ncelab <ERROR_CODE>
I like my compilation build to be free from warnings. Here’s how to solve this warning.
myObj.pixelValue[0] = 0;
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ncvlog: *W,ENUMERR (myChecker.sv,528|34): This assignment is a violation of SystemVerilog strong typing rules for enumeration datatypes.
pixelValue is an enumerated data type like :
typedef enum reg [1:0] {
PV_ONE = 2’h0,
PV_THREE = 2’h1,
PV_FIVE = 2’h2,
PV_TEN = 2’h3
} e_pixel;
e_pixel pixelValue;
Solution :
I have to cast the integer value 2 to e_pixel format before I can assign it to the enumeration variable. It’s called strong typing.
pixelValue = e_pixel’ (2);
but
pixelValue = PV_THREE; // Correct and valid
I came across this strange problem where it started asking for license of Cadence’s Incubation tool.
irun(64): 12.20-s008: (c) Copyright 1995-2013 Cadence Design Systems, Inc.
irun: *W,CSSF: HDL source files with -R option will be ignored.
Incisive_Incubation 1.0 – license unavailable
ncsim: *F,NOLICN: Unable to checkout license for the simulation. (flag – 42) ‘lic_error -18’.
ncsim: Memory Usage – 26.0M program + 19.2M data = 45.3M total
ncsim: CPU Usage – 0.0s system + 0.0s user = 0.0s total (67.9s, 0.0% cpu)
After a lot of probing and wasting of one whole week, I found that the problem was in trying to do coverpoint on a real variable.
real percent;
covergroup cg_ABC;
coverpoint percent {
bins ….
}
endcovergroup
Solution :
I changed it to
int percent;
and simulation stopped asking for Incubation license.
module dut (dut_if _if);
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ncvlog: *E,EXPRPA (dut.v,1|21): expecting a right parenthesis (‘)’) 12.1(IEEE)].
Problem : The code looks correct, but still having problem ?
Solution : One of the reasons could be that you have not used the -sv switch when compiling.
ncverilog -f filelist -sv
shortint j;
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ncvlog: *E,EXPSMC (myClass.sv,106|10): expecting a semicolon (‘;’) [3.2.2(IEEE)].
Problem : very straightforward, you are missing a semicolon, but where ? right above the line shown, @ 105.
function void myClass::myTask ();
int datacnt = 0
shortint j;
`LOG_MSG (log, LS_DEBUG, $sformatf (” A task to distribute data packets”));
Solution
function void myClass::myTask ();
int datacnt = 0;
shortint j;
`LOG_MSG (log, LS_DEBUG, $sformatf (” A task to distribute data packets”));
int repLines = 0;
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ncvlog: *E,BADDCL (mySoC.sv,106|5): identify declaration while expecting a statement
Problem : LOG_MSG should come after declaration of variables
function void myClass::myTask ();
`LOG_MSG (log, LS_DEBUG, $sformatf (“This task will distribute data to all packets”));
int dataCount = 0;
shortint j;
Solution :
function void myClass::myTask ();
int dataCount = 0;
shortint j;
`LOG_MSG (log, LS_DEBUG, $sformatf (“This task will distribute data to all packets”));
eecad 