verilog

A case where === in verilog didn’t work

Baffling

I had a statement like :

if (`TB.myDesign.timer.en === ‘bx)

     $display (” Timer Enable has become x”);

else

    $display (“Timer Enable is not x”);

Upon running simulation, I found the signal timer.en to be x in the waveform and yet, the log showed :

Timer Enable is not x. 

I was baffled for a while, and then figured that the tool was unable to process a statement with no information of bit-size (‘bx) and thought I’ll change it to 1‘bx and voila !  It worked !

 

Solution :  So, make sure you specify the bit size. If it’s a vector [31:0] you need to write 32’bx.